1. FIELD OF THE INVENTION
This invention generally relates to high-volume high-speed digital parallel processing, in particular a multiplier-accumulator integrated circuit array that will accept input operands in two's complement, unsigned magnitude, and mixed modes.
2. DESCRIPTION OF THE RELATED ART
A multiplier-accumulator is a computational device that multiplies two multiplier input terms and sums the product with an accumulator term, providing a final output term. A parallel multiplier has the characteristic of operating on multiple bits within the terms simultaneously, that is, in parallel. High speed parallel multipliers and multiplier-accumulators and their efficient integration into silicon or some other semiconductor substrate have been of interest since the early days of digital computers.
Many arithmetic circuits which are widely used in the digital arts are designed for use with two's complement binary signals. While such signals and the associated circuits are particularly well adapted for performing efficiently under many circumstances, two's complement multiplication often requires the use of specialized circuits for correcting errors or characteristically incomplete results. Attempts have been made to reduce specialized circuitry in two's complement arithmetic circuits. See, for example, U.S. Pat. No. 3,866,030 by inventors Baugh and Wooley for a two's complement parallel array multiplier.
A multiplier-accumulator that can operate equally well across unsigned mode, two's complement mode, and mixed modes is desirable.
It is therefore an object of the present invention to provide a multiplier-accumulator that accepts operand formats in all three of the aforementioned modes.
Although a multiplier-accumulator has speed advantages when compared to equivalent circuits, more speed is always desirable.
The present invention therefore has the object of high speed operation.
It has been recognized for some time that a regular circuit structure is advantageous when implementing it in silicon, as circuit regularity permits a faster layout time (either by hand or by a layout generator). Local interconnection between elements of an integrated circuit, which works well when the circuit is regular, minimizes parasitic capacitance and resistance to provide faster circuit operation.
It is therefore a further object of the present invention to provide multiple-mode multiplier-accumulator which has a high degree of circuit regularity and exploits local interconnection.